1. The Field of the Invention
The present invention relates generally to polishing of surfaces such as glasses, semiconductors, and integrated circuits. More particularly, this invention relates to polishing pads that provide wear analysis during polishing and an indication as to the end of the useful life thereof. A method of using the pad is also disclosed. The method of using detects the "worn out" status of the pad, either by automation or such that an operator of a polishing machine, such as a chemical mechanical polishing machine, for semiconductor devices will see, hear, or otherwise detect the point at which a polishing pad has reached the end of its useful life.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above.
Polishing solutions, polishing pads, and slurries are used in chemical-mechanical planarizing (CMP). With slurries, a part or substrate to be polished is bathed or rinsed in the slurry in conjunction with an elastomeric pad which is pressed against the substrate and rotated such that the slurry particles are pressed against the substrate under load. In a fixed-abrasive pad, an abrasive is contained within the pad itself, and the substrate can be polished in either a wet or a dry application. The technique can be accomplished by mechanical planarization (MP) or by CMP.
The polishing mechanism is a combination of mechanical action and the chemical reaction of the material being polished with the solution. The chemical action oxidizes or otherwise treats the most superficial layer, and the mechanic action shears away the treated material. The lateral motion of the pad causes the abrasive particles to move across the surface of the substrate, resulting in pad wear and volumetric removal of the surface. CMP can involve alternative holding and rotating of a substrate against a wet or dry polishing platen under controlled chemical, pressure and temperature conditions. Typically, CMP uses an aqueous colloidal silica solution as the abrasive fluid. Alternatively, the pad itself will contain all the abrasive embedded within its wear surface.
In the semiconductor industry, CMP is used for a variety of surface planarizations. There are various types of planarizable surfaces on a semiconductor substrate, including conductive and insulating materials, such as oxides, nitrides, polysilicon, monocrystalline silicon, amorphous silicon, and mixtures thereof. The substrate has thereon conductive or non-conductive material or both, and the substrate is generally a semiconductor material, such as silicon.
As circuit densities increase, CMP has become one of the most viable techniques for planarization, particularly to planarize interlevel dielectric layers. In view of this increasing viability, improved methods of CMP are increasingly being sought.
A CMP pad is made by one of several methods. One method is to extrude pad material through a large die, the diameter of which is the diameter of a finished polishing pad. After extrusion, the pad is sliced from the extruded stock. Care is taken to make the slice with uniform thickness across the entire pad. Another method is to make a continuous web, roll, or tape of polishing pad material that is taken up onto a spool. During CMP or MP the pad is incrementally advanced by the operator when it is determined that the pad is worn.
One aspect of CMP in need of improvement is worn-pad detection of the useful life of the polishing pad. This detected point occurs before the pad has worn completely through and must be discovered before the article being polished is irreparably damaged by the underlying polishing platen. Although optimizing speed and throughput of the process for semiconductor manufacture are economic imperatives, avoiding damage to any given substrate that happens to be in the polisher at the time the useful life of the pad has expired is also a desired result.
In general, CMP is a relatively slow and time-consuming process. During the polishing process, semiconductor devices must be individually loaded into a carrier, polished, and then unloaded from the carrier. The polishing step in particular is time consuming and may require several minutes. In past practice, the operator would be required to keep an accounting of the number of device polishings for a given pad and then, based upon past experience, discard or increment the pad before it had completely worn out and damaged the substrate or substrates being polished.
Because semiconductor polishing is in a constant state of flux, different techniques have been developed in the art for increasing the speed and throughput of the CMP process. As an example, more aggressive aqueous solutions have been developed to increase the speed of the polishing step. lighter carrier downforces, pulsed downforces, and higher RPMs for the polishing platen are also used.
Although current polishing techniques are somewhat successful, they may adversely affect the polishing process and the uniformity of the polished surface. Worn-pad detection, for instance, is more difficult to estimate when aggressive solutions and higher carrier downforces are employed. In addition, the polishing process may not proceed uniformly across the surface of the article to be polished. The hardness or composition of an article to be polished or the polishing platen may vary in certain areas. This in turn may cause an article to polish faster or slower in some areas, affecting its global planarity. This problem may be compounded by aggressive solutions, higher carrier downforces, and increased RPMs.
The constant change in semiconductor processing technology and the ever-increasing complexity of substrates and polishing techniques, makes prior art methods more difficult for the operator to estimate when a pad is sufficiently worn. Pad replacement techniques based only upon past experience can result in underuse of the pad or in overuse. Pad underuse wastes valuable pad life and operator time, and pad overuse results in a damaged or destroyed batch of articles being polished.
Another problem that arises in CMP technology is when an irregular pad slice is cut from extruded stock but is undetectable to the naked eye. A routine measurement around the perimeter of a slice with a micrometer will show if the slice has thicker or thinner regions than other regions.
Alternatively, the operator could spend significant time conditioning an irregularly cut pad in order to attempt to obtain a virtually flat pad. Conditioning by prior art methods requires extra time and also requires estimating, because removing the pad from the platen may be destructive to the pad.
Another problem in the prior art is where a polishing platen itself contains a planarity defect such that a high or low spot would cause the pad to prematurely wear through at the defect. In the case of a high spot, the remaining pad has to be wasted because the pad would have to be removed before the article to be polished was destroyed.
Another problem that occurs is irregular wear patterns. These patterns become a weak spot on the polishing pad and become more and more enhanced until a hole wears through the pad before the entire pad surface can be uniformly utilized.
In view of these and other problems of prior art polishing and planarizing processes, there is a need in the art for improved methods of worn-pad detection in polishing operations that is accomplished by improved pad construction.